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| www.fairchildsemi.com RV4141A Low Power Ground Fault Interrupter Description The RV4141A is a low-power controller for AC receptacle ground fault circuit interrupters. These devices detect hazardous current paths to ground and ground to neutral faults. The circuit interrupter then disconnects the load from the line before a harmful or lethal shock occurs. Internally, the RV4141A contains a diode rectifier, shunt regulator, precision sense amplifier, current reference, time delay circuit, and SCR driver. Two sense transformers, SCR, solenoid, three resistors and four capacitors complete the design of the basic circuit interrupter. The simple layout and minimum component count ensure ease of application and long term reliability. Features not found in other GFCI controllers include a low offset voltage sense amplifier eliminating the need for a coupling capacitor between the sense transformer and sense amplifier, and an internal rectifier to eliminate high voltage rectifying diodes. The RV4141A is powered only during the positive half period of the line voltage, but can sense current faults independent of its phase relative to the line voltage. The gate of the SCR is driven only during the positive half cycle of the line voltage. Features * * * * * * * * * * Powered from the AC line Built-in rectifier Direct interface to SCR 500 A quiescent current Precision sense amplifier Adjustable time delay Minimum external components Meets UL 943 requirements For use with 110V or 220V systems Available in an 8-pin SOIC package Block Diagram RV4141A Amp Out - + + VFB - + + - VREF Delay - 4.7K +VS SCR Cap Gnd Line 65-4141-01 REV. 1.0.6 6/30/05 PRODUCT SPECIFICATION RV4141A Pin Assignments Amp Out VFB VREF GND 1 2 3 4 8 7 6 5 Delay Cap SCR Trigger +VS Line 65-4141A-02 Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Supply Current Internal Power Dissipation Storage Temperature Range Operating Temperature Range Junction Temperature Lead Soldering Temperature 10 Sec, SOIC -65 -35 Min Typ Max 10 500 +150 +80 125 260 Units mA mW C C C C Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if the Electrical Characteristics are not exceeded. Thermal Characteristics Parameter JA Thermal resistance SOIC Min Typ 240 Max Units C/W 2 REV. 1.0.6 6/30/05 RV4141A PRODUCT SPECIFICATION Electrical Characteristics Parameters Shunt Regulator (Pins 5 to 4) Regulated Voltage Regulated Voltage Quiescent Current Sense Amplifier (Pins 2 to 3) Offset Voltage Gain Bandwidth Slew Rate Input Bias Current SCR Trigger (Pins 7 to 4) Output Resistance Output Voltage Output Voltage Output Current Reference Voltage (Pins 3 to 4) Reference Voltage Delay Timer (Pins 8 to 4) Discharge/Charge ratio Delay Time (Note 1) Delay Current (ILINE = 1.5mA and TA = +25C, RSET = 650k) Test Conditions I2-3 = 11A ILINE = 750 A, I2-3 = 9A V5-4 = 24V Min 25.0 25.0 -- -200 (Design Value) (Design Value) (Design Value) V7-4 = Open, I2-3 = A I2-3 = 9A I2-3 = 11A V7-4 = 0V, I2-3 = 11A ILINE = 750 A I2-3 = 0/11A C8-4 = 12nF I2-3 = 11A 3.8 0 3.0 400 12.0 1.8 -- 30 -- Typ 27.0 27.0 500 0 3 1.0 30 4.7 0.1 3.8 600 13.0 2.5 2.0 40 14.0 3.0 -- 50 100 5.6 10 4.5 Max 29.0 29.0 -- 200 -- Units V V A V MHz V/S nA k mV V A V A/A ms A Note: 1. Delay time is defined as starting when the instantaneous sense current (I2-3) exceeds 6.5 V/RSET and ending when the SCR trigger voltage V7-6 goes high. REV. 1.0.6 6/30/05 3 PRODUCT SPECIFICATION RV4141A Circuit Operation (Refer to Block Diagram and Figure 1) The precision op amp connected to Pins 1 through 3 senses the fault current flowing in the secondary of the sense transformer, converting it to a voltage at Pin 1. The ratio of secondary current to output voltage is directly proportional to feedback resistor, RSET. RSET converts the sense transformer secondary current to a voltage at Pin 1. Due to the virtual ground created at the sense amplifier input by its negative feedback loop, the sense transformer's burden is equal to the value of RIN. From the transformer's point of view, the ideal value for RIN is 0. This will cause it to operate as a true current transformer with minimal error. However, making RIN equal to zero creates a large offset voltage at Pin 1 due to the sense amplifier's very high DC gain. RIN should be selected as high as possible consistent with preserving the transformer's operation as a true current mode transformer. A typical value for RIN is between 200 and 1000. As seen by the equation below, maximizing RIN minimizes the DC offset error at the sense amplifiers output. The DC offset voltage at Pin 1 contributes directly to the trip current error. The offset voltage at Pin 1 is: VOS x RSET/(RIN + RSEC) Where: VOS = Input offset voltage of sense amplifier RSET = Feedback resistor RIN = Input resistor RSEC = Transformer secondary winding resistance The sense amplifier has a specified maximum offset voltage of 200 V to minimize trip current errors. Two comparators connected to the sense amplifier output are configured as a window detector, whose references are -6.5V and +6.5V, referred to Pin 3. When the sense transformer secondary RMS current exceeds 4.6/RSET the output of the window detector starts the delay circuit. If the secondary current exceeds the predetermined trip current for longer than the delay time a current pulse appears at Pin 7, triggering the SCR. The SCR anode is directly connected to a solenoid or relay coil. The SCR can be tripped only when its anode is more positive than its cathode. The recommended value for RLINE is 24 k to 47 k for 110V systems and 47 k to 91 k for 220V systems. When RLINE is 47 k the shunt regulator current is limited to 3.6 mA. The recommended maximum peak line current through RLINE is 10 mA. GFCI Application (Refer to Figure 1) The GFCI detects a ground fault by sensing a difference current in the line and neutral wires. The difference current is assumed to be a fault current creating a potentially hazardous path from line to ground. Since the line and neutral wires pass through the center of the sense transformer, only the differential primary current is transferred to the secondary. Assuming the turns ratio is 1:1000 the secondary current is 1/1000th the fault current. The RV4141A's sense amplifier converts the secondary current to a voltage which is compared with either of the two window detector reference voltages. If the fault current exceeds the design value for the duration of the programmed time delay, the RV4141A will send a current pulse to the gate of the SCR. Detecting ground to neutral faults is more difficult. RB represents a normal ground fault resistance, RN is the wire resistance of the electrical circuit between load/ neutral and earth ground. RG represents the ground to neutral fault condition. According to UL 943, the GFCI must trip when RN = 0.4, RG = 1.6 and the normal ground fault is 6 mA. Assuming the ground fault to be 5 mA, 1 mA and 4 mA will go through RG and RN, respectively, causing an effective 1 mA fault current. This current is detected by the sense transformer and amplified by the sense amplifier. The ground/ neutral and sense transformers are now mutually coupled by RG, RN and the neutral wire ground loop, producing a positive feedback loop around the sense amplifier. The newly created feedback loop causes the sense amplifier to oscillate at a frequency determined by ground/neutral transformer secondary inductance and C4. Typically it occurs at 8 KHz. C2 is used to program the time required for the fault to be present before the SCR is triggered. Refer to the equation below for calculating the value of C2. Its typical value is 12 nF for a 2 ms delay. RSET is used to set the fault current at which the GFCI trips. When used with a 1:1000 sense transformer, its typical value is 1 M for a GFCI designed to trip at 5 mA. RIN should be the highest value possible which ensures a predictable secondary current from the sense transformer. If RIN is set too high, normal production variations in the transformer permeability will cause unit to unit variations in the secondary current. If it is too low, a large offset voltage error at Pin 1 will be present. This error voltage in turn creates a trip current error proportional to the input offset voltage of the sense amplifier. As an example, if RIN is 500, Supply Current Requirements The RV4141A is powered directly from the line through a series limiting resistor called RLINE, its value is between 24 k and 91 k. The controller IC has a built-in diode rectifier eliminating the need for external power diodes. 4 REV. 1.0.6 6/30/05 RV4141A PRODUCT SPECIFICATION RSET is 1 M, RSEC is 45 and the VOS of the sense amplifier is its maximum of 200 V, the trip current error is 5.6%. The SCR anode is directly connected to a solenoid or relay coil. It can be tripped only when its anode is more positive than its cathode. It must have a high dV/dt rating to ensure that line noise (generated by electrically noisy appliances) does not falsely trigger it. Also the SCR must have a gate drive requirement less than 200 A. C3 is a noise filter that prevents high frequency line pulses from triggering the SCR. The relay solenoid used should have a response time of 3 ms or less to meet the UL 943 timing requirement. minimum delay time required to prevent nuisance tripping. This will typically be 1 to 2 ms. The value of C2 required to provide the desired delay time is: C2 = 6 x T where: C2 is in nF T is the desired delay time in ms. The value of RSET to meet the nominal ground fault trip current specification is: 4.6 x N R SET = --------------------------------------------------------------I FAULT x COS 180 ( T P ) where: RSET is in k T is the time delay in ms P is the period of the line frequency in ms IFAULT is the desired ground fault trip current in mA RMS N is the number of sense transformer secondary turns. This formula assumes an ideal sense transformer is used. The calculated value of RSET may have to be changed up to 30% to when using a non-ideal transformer. Sense Transformers and Cores The sense and ground/neutral transformer cores are usually fabricated using high permeability laminated steel rings. Their single turn primary is created by passing the line and neutral wires through the center of its core. The secondary is usually from 200 to 1500 turns. Transformers may be obtained form Magnetic Metals, Inc. (www.magmet.com) Calculating the Values of RSET and C2 Determine the nominal ground fault trip current requirement. This will be typically 5 mA in North America (117V AC) and 22 mA in the UK and Europe (220V AC). Determine the RTEST Mov Sense Transformer 1:1000 5 Ring Steel Core Phase Line Neutral 15K Press to Test Normally Closed Latching Contacts Grounded Neutral 1:200 Load Solenoid C4 RN 0.4 RB 20K R IN 470 1000 pF C1 10 nF C2 1 8 7 2 3 4 12 nF CF + 1F 35V 1N4004 Q1 TAG X0103DA C3 10 nF RG 1.6 Fault Resistance Not Part of Application R SET 1.1 Meg R LINE 24K 1W RV4141A 6 5 GFCI 65-4141A-03 Note: 1. Portions of this schematic are subject to U.S. patents 3,878,435 and Re. 30,678. Figure 1. GFI Application Circuit REV. 1.0.6 6/30/05 5 PRODUCT SPECIFICATION RV4141A Mechanical Dimensions 8-Lead SOIC Package Inches Min. A A1 B C D E e H h L N ccc .053 .004 .013 .008 .189 Max. .069 .010 .020 .010 .197 Millimeters Min. 1.35 0.10 0.33 0.20 4.80 Max. 1.75 0.25 0.51 0.25 5.00 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. Symbol .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27 3 6 8 5 E H 1 4 D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C h x 45 C e L 6 REV. 1.0.6 6/30/05 PRODUCT SPECIFICATION RV4141A Ordering Information Part Number RV4141AMT Package 8-lead Plastic SOIC Pb-Free No Operating Temperature Range -35C to +80C Packing Method Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 6/30/05 0.0m 001 Stock#DS2004141A 2005 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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